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ISL22316WMUEP
Single Digitally Controlled Potentiometer (XDCPTM)
Data Sheet December 17, 2007 FN6622.0
Low Noise, Low Power I2C(R) Bus, 128 Taps
The ISL22316WMUEP integrates a single digitally controlled potentiometer (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up, the device recalls the contents of the DCP's IVR to the WR. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments and signal processing.
Features
* Specifications per DSCC VID V62/08603-01XB * Full Mil-Temp Electrical Performance from -55C to +125C * Controlled Baseline with One Wafer Fabrication Site and One Assembly/Test Site * Full Homogeneous Lot Processing in Wafer Fab * No Combination of Wafer Fabrication Lots in Assembly * Full Traceability Through Assembly and Test by Date/Trace Code Assignment * Enhanced Process Change Notification * Enhanced Obsolescence Management * Eliminates Need for Up-Screening a COTS Component * 128 Resistor Taps * I2C Serial Interface - Two Address Pins, Up To Four Devices/Bus * Non-volatile Storage of Wiper Position * Wiper Resistance: 70 Typical @ 3.3V * Shutdown Mode * Shutdown Current 5A Max * Power Supply: 2.7V to 5.5V
Device Information
The specifications for an Enhanced Product (EP) device are defined in a Vendor Item Drawing (VID), which is controlled by the Defense Supply Center in Columbus (DSCC). "Hot-links" to the applicable VID and other supporting application information are provided on our website.
Pinout
ISL22316WMUEP (10 LD MSOP) TOP VIEW
SCL SDA A1 A0 SHDN 1 2 3 4 5 10 9 8 7 6 VCC RH RW RL GND
* 10k Total Resistance * High Reliability - Endurance: 1,000,000 Data Changes Per Bit Per Register - Register Data Retention: - 10 years @ T +125C - 15 years @ T +90C - 50 years @ T +55C * 10 Ld MSOP
Ordering Information
VENDOR PART NUMBER (Notes 1, 2) ISL22316WMUEP NOTES: 1. Add "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. Devices must be procured to the VENDOR PART NUMBER. VENDOR ITEM DRAWING PART MARKING V62/08603-01XB 2316M RESISTANCE OPTION (k) 10 TEMP. RANGE (C) PACKAGE PKG. DWG. #
-55 to +125 10 Ld MSOP M10.118
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL22316WMUEP Block Diagram
VCC
SCL SDA A0 A1 I2C INTERFACE
POWER-UP INTERFACE, CONTROL AND STATUS LOGIC
RH
WR
RW
RL SHDN NON-VOLATILE REGISTERS
GND
Pin Descriptions
MSOP PIN 1 2 3 4 5 6 7 8 9 10 SYMBOL SCL SDA A1 A0 SHDN GND RL RW RH VCC Open drain I2C interface clock input Open drain Serial data I/O for the I2C interface Device address input for the I2C interface Device address input for the I2C interface Shutdown active low input Device ground pin "Low" terminal of DCP "Wiper" terminal of DCP "High" terminal of DCP Power supply pin DESCRIPTION
2
FN6622.0 December 17, 2007
ISL22316WMUEP Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -CL L1 4X R1 R 0.20 (0.008) ABC E
INCHES SYMBOL A A1 A2 b c D
4X
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 4.75 0.40 10 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 0 12/02
MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 0.187 0.016 10 0.003 0.003 5o 0o
MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 0.199 0.028
INDEX AREA
E1 e E L L1 N R R1
-B-
A
A2
0.020 BSC
0.50 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
SIDE VIEW
15o 6o
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 3
FN6622.0 December 17, 2007

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